The "Cross-Check" test structure allows up to 100 percent electrical testing of very large scale integrated circuits by the addition of an array of test points to the integrated circuit (IC) being tested. This test structure and its method of operation are described in U.S. Pat. No. 4,749,947 to T. Gheewala entitled "GRID-BASED, "CROSS-CHECK" TEST STRUCTURE FOR TESTING INTEGRATED CIRCUITS." That patent is hereby incorporated in its entirety into this application.
For the purposes of this application, the structure should be understood to consist of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of the probe- and sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe- and sense-lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines.
The use of the "Cross-Check" test structure generates a tremendous volume of test data. Typically, the output node of every combinatorial logic gate in the IC is tested every clock cycle. Data compression is commonly used to reduce this test data to a manageable quantity. One of the most common forms of data compression requires the use of a Multiple Input Linear Feedback Shift Register ("MISR"). When a MISR is used for data compression with a "Cross-Check" test grid, test data from the sense lines of the "Cross-Check" grid is loaded in parallel into the MISR. After the initial data is loaded, data in the MISR is exclusive ORed ("XORed") with new data generated during each subsequent clock cycle. Data is shifted one bit within the MISR every clock cycle. Various MISR output bits may be further XORed and fed back to any input or inputs of the MISR.
As shown in FIG. 1, MISR 12 has 8 registers labelled 1 through 8, the outputs of registers 5 and 8 being XORed, the result of which is XORed with the output of register 1. Finally, the result from this XOR operation is fed back to the input of register 1. XOR circuits 13 are coupled to the output of the previous register and the input for each register, except, as noted, register 1, and perform the "XOR" function. Alternative embodiments could operate with cellular automata as long as appropriate modification is made.
A possible problem with data compression is the unintentional concealment of errors or "masking". Any single error will cause the data on the sense line receiving that error to be opposite to its correct value. In turn this will cause one bit in the MISR to be similarly incorrect. Given the nature and structure of an MISR, such an error will propagate, spreading to multiple locations with time as the data within the MISR is fed back to the MISR's inputs. However, if another error is detected and loaded into the same location in the MISR as that containing the previous error, the two errors may cancel one another through the XOR operation. Thus, the second error "masks" the first. In addition to such single bit masking of errors, multiple bit masking of errors is also possible, albeit much less likely.
Within the context of "Cross-Check" testing, two or more purely random errors have a very low probability of masking one another. Two unlikely conditions must occur to cause such a masking of an error.
First, the error which will mask the first error must be detected during every, but only every, test cycle within which the first error is detected. These are the only times that the second error can mask the first error and not itself cause a new, detectable error. For example, if the first error consists of a short to the power supply voltage V.sub.DD, which would appear as a "stuck-at-one" error, the error will only be detectable when the correct logic output should be a logic zero. During the test cycles that the logic level is expected to be a logic one, this type of error will not be detectable.
Second, the error must be in the proper physical location to mask the first error. For example, assume a circuit with 10,000 test points and 1,000 test cycles. If, on the average, an error is XORed and fed back to the MISR input after four MISR clock cycles, there are a maximum of four different physical locations (the four locations where the error is stored before being fed back) where an error could be masked before it propagates into multiple locations. The probability of this occurring is 4 in 10,000 during any given clock cycle. For the two errors to mask one another, they must additionally be in the same detectable or undetectable state during every clock cycle. As the errors are unrelated, there is only a 50% chance that the second error will be in the correct state to mask, or not mask, the first error. The probability of masking an error under these conditions can be given as: EQU P=(4/10,000) (0.5.sup.1,000).apprxeq.1.times.10.sup.-300
which is so small as to be negligible.
However, errors may be related because of their interconnection (logical proximity) in the IC. In such cases, the probability of masking an error is much higher. For example, a node shorted to V.sub.DD will be stuck at logic level one. If this node is coupled to the input of an inverter, the output of the inverter will always be zero. Thus every time the first error is detected, the second one also is detected. If the output of the inverter is in the proper location to mask the first error, it will do so every time. Additionally, these nodes will drive other logic elements whose logic states must also be taken into account.
As the purpose of the software used to lay out an IC is to minimize the physical interconnect length between features and components, the probability of logically proximate features and components being physically close to one another on the IC is high. In such cases the probability of physical locations allowing masking of an error is commonly between 2 and 10 percent.
It is also a necessary prerequisite for masking an error that the error not propagate to other logically proximate nodes. For any given test cycle, the probability of the necessary non-propagation is on the order of 10 to 50 percent.
Finally, the number of nodes likely to have the condition such that the cancelling error pattern is the only pattern applied has also been found to be from one to ten percent. The final probability of masking an error therefore falls within the range of EQU P.sub.1 =(0.02) (0.10) (0.01)=0.002% and EQU P.sub.2 =(0.10) (0.50) (0.1%)=0.5%,
with the median probability P.sub.3 =0.05%.
The probability of masking an error reduces the quality of the test, increasing the probability that a bad device will be deemed good. These levels of test are insufficient to assure high shipment lot quality.
The percentage of defective units (DU) in a lot due to masking an error is given by the formula:
______________________________________ DU = (# bad)/[# Good + # Bad] (# Good) = process yield (Y) (# Bad) = (1 - Y)P, where P equals the probability of a bad device passing the test due to masking an error. ______________________________________
Therefore, EQU DU=(1-y)P/(Y+(1-Y)*(P))
For the case where Y=10% and P=P.sub.2 (see above): EQU DU=(1-0.1)(0.005)/(0.1+(1-0.1)(0.005))=4.3%
The last calculation shows that in some not unlikely scenarios, the risk of a defect in the IC being undetected by the "Cross-Check" circuit is not acceptably small.
Thus, there is a need for either new circuitry or new methods of use which will, when combined with "Cross-Check" testing circuitry, substantially reduce the possibility that errors will be masked.